Volume : VI, Issue : III, March - 2017

Dietary Challenges faced by middle income group post bariatric patients as compared to the affluent class patients: Clinical study done in Indian Government health setup

Tiwari P. , Chaubey S. , Srivastava A.

Abstract :

 Digital Signal Processing (DSP) applications widely use complex arithmetic operations. In general, a separate adder and a multiplier are used to perform Add-Multiply operation.  An efficient Fused Add-Multiply Unit is implemented using the Radix-8 Modified Booth Recoder. The Modified Booth Recoder design is based on the redundant logic and constant-time addition. In this proposed paper the Xilinx Vivado IDE Tool is used for synthesis and is used for simulation. Instead of deriving the adder output as in conventional methods, the recoder recodes the adder input directly to MB form thus decreasing delay. The multiplier unit uses the Radix-8 Modified Booth algorithm. On analyzing the Radix-8 FAM unit, it has been observed that the newly modified design yields better performance in terms of area and delay. We are designing our architecture in Verilog HDL code using Vivado 14.3 and implemented on Zynq Board(FPGA).

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Article: Download PDF    DOI : https://www.doi.org/10.36106/gjra  

Cite This Article:

N.VIVEK, T.RAJESH, FPGA IMPLEMENTATION OF AN EFFICIENT FUSED ADD-MULTIPLY UNIT, GLOBAL JOURNAL FOR RESEARCH ANALYSIS : Volume-6, Issue-3, March‾2017

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