Dual Ethernet Frame Detector Layout & Verification

Sharat Chandra Musham; Abhishek Banerjee; Bala Chintamneedi

Volume : VI, Issue : VII, July - 2017

Dual Ethernet Frame Detector Layout & Verification

Sharat Chandra Musham, Abhishek Banerjee, Bala Chintamneedi

Abstract :

The purpose of the project is to place the cells and route in order to implement the Ethernet Frame detector developed for project 3. To achieve the over 100 cell requirement, we implemented Dual Ethernet Frame Detector (DEFD). The idea is to design and implement a circuit which has practical significance and yet simple to design and implement so that the focus will be more on learning the tools. Finally Pathmill was used to find out the worst delays from inputs to outputs.