Volume : VII, Issue : V, May - 2017

An Overview of Unified Verification Methodology

P. N. Jayanthi, Pooja Ganesh, Nikhil Guptha

Abstract :

 In today’s markets, industries have to focus on quality of their products to retain their competitive edge. It is a well–known fact that about one third of the total cost in the development of a new chip is devoted to hardware debugging and testing. Design verification is an important step to achieve reliability. Even a small defect in any part or block of a SoC can lead to improper functionality of the chip. Most of the existing verification methodologies involve providing test vectors as input and this may not cover all test cases in an exhaustive manner. Hence, a novel approach that involves randomization of test vectors proves to be a solution in this case. This paper provides  the unified verification process and its importance. And   the different aspects of verification are discussed for a given chip. 

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Article: Download PDF   DOI : 10.36106/ijar  

Cite This Article:

P. N. Jayanthi, Pooja Ganesh, Nikhil Guptha, An Overview of Unified Verification Methodology, INDIAN JOURNAL OF APPLIED RESEARCH : Volume‾7 | Issue‾5 | May‾2017

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