Volume : VI, Issue : III, March - 2017

FPGA IMPLEMENTATION OF HIGH SPEED LOW POWER 16 BIT MULTIPLIER

P. Rama Krishna, G. Priyanka

Abstract :

 The main objective of the project is to design Vedic Multiplier and Square Architectures based upon ancient Indian Vedic mathematics sutras for DSP applications. In this work, all the partial products are adjusted using concatenation operation and are added by using single carry save adder instead of two adders at different stages. The high speed Vedic multiplier architecture is then used in the squå modules. The key to our success is that only one Vedic Multiplier is used instead of four multipliers. The reduced number of computations in multiplication due to adjusting using concatenation operation and one carry save adder only, the designed multiplier offers significant improvement in speed, reduces delay. The Proposed method is Coded in Verilog, Synthesized and Simulated using Xilinx ISE Tool 13.2. We are designing our architecture in Verilog HDL code and also simulated by using Vivado 2015.2 tool and Hardware Implementation on ZYNQ Board(FPGA). The Project functionality input and output to the system is in digital data. And the process expected to be done in the system is Multiplication and Squå. The specifications of vedic multiplier and square architectures are of 32bits digital data input bit size and 64bits digital data output bit size.

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Article: Download PDF    DOI : https://www.doi.org/10.36106/gjra  

Cite This Article:

T.SRAVANTHI DEVI, A.MADHU SUDHAN, FPGA IMPLEMENTATION OF 32-BIT VEDIC MULTIPLIER AND SQUARE ARCHITECTURES, GLOBAL JOURNAL FOR RESEARCH ANALYSIS : Volume-6, Issue-3, March‾2017

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