Global Journal For Research Analysis (GJRA)

Dr. Bhupendra Patil; Dr. Suwarna Patil; Vivek Karale; Dr. Vilas Malkar

Volume : VI, Issue : III, March - 2017

Jaundice In Pregnancy And Fetal Outcome

Dr. Bhupendra Patil, Dr. Suwarna Patil, Vivek Karale, Dr. Vilas Malkar

Abstract :

The router is a "Robust Router" consist of one input port from which the packet enters. It has three output ports where the packet is driven out. Packet contains three parts. They are Header, and data and frame check sequence. Packet width is of 8 bits and length of the packet transferring can be between 1 to 63 bytes. The switch drives the packet to respective ports based on this destination address of the packet. Each output has 8 bit unique port address. If the destination address of the packet matches the port address, then the switch drives the packet to the output port, length of the data is of 8 bits. In this proposed paper the Xilinx Vivado IDE Tool is used for synthesis and is used for simulation .In the proposed design the FSM is designed with reduced number of states, due to reduction of states the amount of time to produce the response became less obviously the frequency is improved. The Robust Router design is done by using of the 3 blocks, the blocks are 8-Bit Register, Router controller(FSM) and output block which is consists of 3 fifo‘s combined together are store packet of data and when you want to data that time the data read from the FIFO‘s. In this router design has three outputs that is 8-Bit size and one 8_bit data port it using to drive the data into router we are using the global clock and reset signals, and the err signal and suspended data signals are output�s of the router .The FSM controller gives the err and suspended_data_in signals and We are designing our architecture in Verilog HDL code using Vivado 14.3 and implemented on Zynq Board(FPGA).