Volume : V, Issue : V, May - 2016


G. M. Anitha Priyadarshini, Dr. Gae Sathish Kumar

Abstract :

 The signals in this present reality are analog in nature for instance light, solid, video and so on. In request to accomplish digital signal, we have to change over the analog signal into digital form by utilizing a circuit called analog-to-digital converter. The interest for the converter is situated on area, speed, power of the converters. In request to accomplish these optimization‘s we are designing a comparator, a Wallace tree adder and an inverse Gaussian function. Here, speed can be improved by developing an analog comparator from two cross-coupled 3-input digital NAND gates. To reduce power utilization we are using Wallace tree adder, which is normally used for high speed and efficient one‘s addition. Here, the fundamental reason for inverse Gaussian function is to take out the noise present in the output furthermore to reconstruct the digitalized signal into its original form. So as to outline a flash ADC, all blocks including the comparators, the ones adder, and the piece wise inverse Gaussian function are designed in Verilog HDL. To implement this architecture on FPGA we are using Vivado 2014.2.

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Article: Download PDF    DOI : https://www.doi.org/10.36106/gjra  

Cite This Article:

G. M. Anitha Priyadarshini, Dr. GAE Sathish Kumar PROFICIENT 15-BIT FLASH ADC DESIGN USING WALLACE TREE ADDER Global Journal For Research Analysis, Vol: 5, Issue : 5 MAY 2016

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