Volume : II, Issue : I, January - 2013
A new Parallel Counter Architecture with Reduced Transistor Count for Power and Area Optimization
Dr. K. Babulu , K. Venkateswara Rao
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DOI : https://www.doi.org/10.36106/paripex
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A NEW PARALLEL COUNTER ARCHITECTURE WITH REDUCED TRANSISTOR COUNT FOR POWER AND AREA OPTIMIZATION, Dr. K.Babulu , K.Venkateswara Rao GLOBAL JOURNAL FOR RESEARCH ANALYSIS : Volume-2 | Issue-1 | January-2013
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A NEW PARALLEL COUNTER ARCHITECTURE WITH REDUCED TRANSISTOR COUNT FOR POWER AND AREA OPTIMIZATION, Dr. K.Babulu , K.Venkateswara Rao GLOBAL JOURNAL FOR RESEARCH ANALYSIS : Volume-2 | Issue-1 | January-2013