Volume : I, Issue : VI, November - 2012

A Generic Design for Defect Diagnosis of Memories

Shaik. Siraj, Sk. Saidulu

Abstract :

This paper mainly designed and implemented Memory BIST targeting the System–on–chip (SOC). Failure analysis and diagnosis of memory cores plays a key role in SOC product development and yield ramp–up. Diagnosis technique plays a key role for catching the design and manufacturing failures and improving the overall yield and quality. The increasing time–to–volume pressure on semiconductor products calls for new development flow that enables to reach a profitable yield level as soon as possible. MBIST is designed in such a way that it can be used for any number of memories depending upon the application. We are going for a modified MARCH algorithm, using which we can test the memory and not only locate fault cells but also identify their types.This algorithm proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. Algorithm: Ý (w0); Ý ( r0,w1,r1); Ý (w5,r5); ß (r5,wa,ra);  

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Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

SHAIK.SIRAJ, SK.SAIDULU A Generic Design for Defect Diagnosis of Memories International Journal of Scientific Research, Vol.I, Issue.VI Nov 2012

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