An Alternative Logic Approach to Implement  Energy Efficient 90–Nm  Cmos Full Adders

Onteru. Anjaneyulu; Kallepelli Sagar; C. V. Krishna Reddy

Volume : II, Issue : X, October - 2013

An Alternative Logic Approach to Implement Energy Efficient 90–Nm Cmos Full Adders

Onteru. Anjaneyulu, Kallepelli Sagar, C. V. Krishna Reddy

Abstract :

This paper presents power analysis of the seven full adder cells reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. In this we mainly present two proposed high–speed and low–power full–adder cells designed with an alternative internal logic structure and pass–transistor logic styles that lead to have a reduced power delay product (PDP). The existed standard full adders and the proposed full adders are designed and showed the better result comparison. This paper describes how the proposed full adders are better in contrast to the standard full adders. All the full–adders were designed with a 90–nm CMOS technology, and simulated using mentor graphics EDA tool with BSIMv3 (model49).Post–layout simulations show that the proposed full–adders outperform its counterparts exhibiting an average PDP advantage