An Evaluation of Power Analysis Attacks on Asynchronous Substitution Box

S. Muhammad Jakheer; Shaik Jaffar; Syed Jahangir Badashah

Volume : II, Issue : XI, November - 2013

An Evaluation of Power Analysis Attacks on Asynchronous Substitution Box

S. Muhammad Jakheer, Shaik Jaffar, Syed Jahangir Badashah

Abstract :

In this paper we demonstrate implementation of less–power asynchronous Advanced Encryption Standard substitution box design capable of being resistant to the side channel attack. A specified side channel attack standard evaluation field–programmable gate array board is used to implement both asynchronous and synchronous substitution box designs. This asynchronous substitution box, is based on a self–time logic referred as null convention logic which supports beneficial properties for resisting side channel attack dual–rail encoding, clock free and monotonic transitions. These properties make it difficult for an attack to decipher secret keys embedded in the cryptographic circuit of FPGA board. Comparisons on the resistance to side channel attack of both the original and proposed substitution box design are presented, using correlation power analysis and differential power analysis attacks. The power measurement results showed that the null convention logic substitution box had 24%–28% lower than total power consumption, was effective against differential power analysis and correlation power analysis attacks. An important factor of successfully implementing differential power analysis or correlation power analysis attacks, the number of power traces, are also analyzed in the paper