Volume : VI, Issue : X, October - 2017

DESIGN AND ANALYSIS OF A SRAM CELL USING PULSED LATCH CIRCUIT

N Namrata, Khemraj Deshmukh

Abstract :

 This paper describes a low power and delay effective SRAM (Static Random Access Memory) cell using pulsed latch circuit. The pulsed latch circuit consist of two cross coupled inverters and three NMOS transistors. In the proposed design, two access transistors present in the basic 6T SRAM cell are replaced by the pulsed latch circuit. The conventional and proposed SRAM cell, both the cells are designed in 65nm and 130nm CMOS technology with 1.0V and 1.5V power supply in Tanner tool v16.0. In comparison with the conventional SRAM cell, the proposed design yields better results in terms of power and speed. In the proposed design delay reduces drastically as compared to that of the conventional SRAM cell. < clear="all" style="page–eak–before:always; mso–eak–type:section–eak" />

Keywords :

Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

N Namrata, Khemraj Deshmukh, DESIGN AND ANALYSIS OF A SRAM CELL USING PULSED LATCH CIRCUIT, INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH : Volume-6 | Issue-10 | October-2017

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