Volume : I, Issue : VI, November - 2012

Design of AMBA 3.0 (AXI) Bus based SoC

D. Neelavathi

Abstract :

System–on–a–Chip (SoC) design has become more and more complexly. Because difference functions components or IPs (Intellectual Property) will be integrated within a chip. The challenge of integration is “how to verify on–chip communication properties”. Although traditional simulation–based on–chip bus protocol checking bus signals to obey bus transaction behavior or not, however, they are still lack of a chip–level dynamic verification to assist hardware debugging. We proposed a rule based synthesizable AMBA AXI protocol checker. The AXI protocol checker contains 44 rules to check on–chip communication properties accuracy. In the verification strategy, we use the Synopsys VIP (Verification IP) to verify AXI protocol checker. In the experimental results, the chip cost of AXI protocol checker is 70.7K gate counts and critical path is 4.13 ns (about 242 MHz) under TSMC 0.18um CMOS 1P6M Technology. | The benefits of using rule–based design include improving observability, reducing debug time, improving integration through correct usage checking, and improving communication through documentation. In the final purpose, increasing design quality while reducing the time–to–market and verification costs. We anticipate that the AMBA AXI protocol checking technique will be more and more important in the future. Hence, we propose a synthesizable AMBA AXI protocol checker with an efficient verification mechanism based on rule checking methodology. There are 44 rules to check the AMBA AXI protocol that provide AXI master, slave, and default slave protocol issues.

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Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

D.Neelavathi Design of AMBA 3.0 (AXI) Bus based SoC International Journal of Scientific Research, Vol.I, Issue.VI Nov 2012

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