Volume : III, Issue : V, May - 2014

Fpga Implementation of Variable–Latency Speculating Booth Multiplier (Vlsbm )

Bency John

Abstract :

Data hazards cause major pipeline performance degradation for data–intensive computing processes. To improve the performance of the pipeline efficiency, a high–speed VLSBM is proposed. This is done by successively performing a speculating and correcting phase. To decrease the critical path, the VLSBM partial products are divided into the –bit least significant part (LSP) and the –bit most significant part (MSP). The estimation function predicts the carry to the MSP, thereby permitting independent calculation of the partial–product accumulation of parts. If a carry prediction is true, the data dependence is hidden and the correcting phase is bypassed, thereby make sure that the potential speed–up of the pipelined data path. When a miss–carry prediction occurs, the speculation is flushed and the correcting phase is performed to obtain the exact multiplication. Verilog HDL is used as a description language and Xilinx ISE sim as simulation tool for implementation. Xilinx Spartan 3 XC3S200 Field Programmable Gate Array (FPGA) was chosen as a Hardware Platform for the System Implementation.

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Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

Bency John Fpga Implementation of Variable-Latency Speculating Booth Multiplier (Vlsbm ) International Journal of Scientific Research, Vol.III, Issue. V, May 2014

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