Volume : I, Issue : VI, November - 2012

Hardware Implementation Of Iris Matching

Bethuna

Abstract :

Now a days, necessity of identifying users of secure facilities or other resources becomes very important to prevent fraudulent access. Biometrics is emerging as a technology that provides a higher level of security, efficiency and convenience than traditional ID or password methods for user authentication. A biometric system is essentially a pattern recognition system that recognizes a person based on a feature vector derived from a specific physiological or behavioural characteristic that a person posses. Human has many biometric features such as fingerprint, hand geometry, gait, face, voice and iris. Among these Iris recognition is especially attractive due to stability of the iris texture patterns with age and health conditions. However, the iris recognition algorithms are currently implemented on general purpose sequential processing systems, such as generic central processing units (CPUs). In this paper, we present a parallel processing alternative using field–programmable gate arrays (FPGAs), offering an opportunity to increase speed of the resulting system. Matching part of the iris recognition algorithm has been implemented using Verilog HDL targeting low–cost Spartan 3AN FPGA, achieving significant reduction in execution time when compared with a conventional software based applications. The Hamming distance is employed for classification of iris templates, and two templates were found to match if hamming distance between them is less than the threshold value. The goodness of the proposed approach has been tested using iris images from the CASIA database.

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Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

Bethuna Hardware Implementation Of Iris Matching International Journal of Scientific Research, Vol.I, Issue.VI Nov 2012

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