Volume : VI, Issue : VIII, August - 2017

Implementation of Frequency Multiplier Using DPLL and its BIST

Degala Krishna Chitanya Tarun, D. Raja Ramesh

Abstract :

 The clocks are required to synchronize between Integrated Circuits and functional blocks and mainly to progress the operations of digital systems for excellence in performance. For each architecture of the processor and the processing technology generation, the frequencies and data rates of clocks have been increasing gradually. In order to generate the on–chip clocks to have well–timed, Phase locked–loops (PLLs) can be oadly used.  The bandwidth of the system loop can be changed easily in Fully Digital PLLs. When compared to the traditional designs such as charged–pump PLLs, All DPLLs are more suitable for the monolithic design with other circuits. Any variations in the process cannot disturb the functionality of the All–Digital PLLs and so can be applied easily to any technology. This DPLL is based on a self–biased architecture that automatically tracks process, voltage, and temperature variations, producing stable and consistent DPLL performance over a oad range of operating conditions.   Frequency agility is achieved with programmable dividers for the reference clock, feedback clock, and voltage–controlled–oscillator (VCO) output.  A bypass multiplexer (MUX) allows either the reference clock or the PLL VCO output to be output from the PLL.  Lock detect circuitry indicates the DPLL lock state. The experimental results of DPLL with waveforms are shown for a 0.2GHz DPLL. The blocks of the DPLL, synthesized from the hardware description language (HDL) are also provided. The static timing analysis of the DPLL is also done by using dc shell. The Built–in Self–Test (BIST) circuit is generated which tests the parameters include RMS jitter, loop gain, lock range, lock time and the natural frequency is calculated from the loop gain which are done by using Tessent Tool.

Keywords :

Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

Degala Krishna Chitanya Tarun, D. Raja Ramesh, Implementation of Frequency Multiplier Using DPLL and its BIST, INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH : VOLUME-6 | ISSUE-8 | AUGUST‾2017

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