Volume : III, Issue : V, May - 2014

Improved Performance in R–Sram Design

Abitha Aboobacker, Sajitha A. S

Abstract :

This paper proposes an SRAM memory cell which embeds ROM data for faster and simpler implementation of certain application such as DSP, math function evaluation, built in self test. On–chip tables stored as ROM can significantly improve the performance with no area penalty and power overhead. Standard 6T and 8T SRAM cells are embedded with ROM data by adding an extra wordline. Here the connectivity between wordlines(WL) and access transistors determines the ROM data. R–SRAM operates in SRAM as well as ROM mode.ROM data cannot be retrieved during SRAM mode.ROM data can retrieved after two special write  steps which depends on connectivity of WLs. A 4KB memory is implemented and tested for functionality

Keywords :

Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

Abitha Aboobacker, Sajitha A.S Improved Performance in R-Sram Design International Journal of Scientific Research, Vol.III, Issue. V, May 2014

Number of Downloads : 152

References :