MATRIX MULTIPLIER DESIGN AND SIMULATION FOR FLOATING POINT, NEGATIVE VALUE AND REAL NUMBERS

Ms. Swati C. Hadke; Prof. Sanjay Tembhurne

Volume : IV, Issue : XII, December - 2015

MATRIX MULTIPLIER DESIGN AND SIMULATION FOR FLOATING POINT, NEGATIVE VALUE AND REAL NUMBERS

Ms. Swati C. Hadke, Prof. Sanjay Tembhurne

Abstract :

Matrix multiplication is the kernel operation used in many image and signal processing applications. In this paper, we present the design and Field Programmable Gate Array (FPGA) implementation of matrix multiplier architectures for use in image and signal processing applications. The designs are optimized for speed which is the main requirement in these applications. First design involves computation of dense matrix vector multiplication which is used in image processing application. The design has been implemented on Virtex–4 FPGA and the performance is evaluated by computing the execution time on FPGA. Implementation results demonstrate that it can provide a throughput of 16970 frames per second which is quite adequate for most image processing applications. Our proposed scheme improves the energy efficiency of the baseline architecture by double precision floating point matrix multiplication. Matrix multiplication computation is one of the important special purpose arithmetic operations for solving large numerical problems. It is very inefficient if the computation is done by software on the core central processing unit. The hardware implementation of such a processor is desirable but inevitably faces the limitation of the amount of VLSI area available. An excessive amount of VLSI area usage for such a processor would impact both cost and performance.