Volume : III, Issue : V, May - 2014

Power–Efficient Dual–Edge Triggered Sense–Amplifier Flip–Flop–Based Driving Circuit For Glitch–Free Nand–Based Dcdl

Chithra. V. H

Abstract :

Digitally controlled delay line (DCDL) is a digital circuit used to provide the desired delays for a circuit whose delay is controlled by a digital controlled word. Glitches are the most considerable factor that limits the use of DCDL in many applications. The glitch–free NAND–based circuit eliminates the glitches of DCDL. This circuit uses control bits that can be generated by using dual edge–triggered flip–flop. In the proposed method, power consumption of dual edge–triggered sense–amplifier flip–flop has been reduced using clock–gated sense–amplifier flip–flop.

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Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

Chithra. V.H Power-Efficient Dual-Edge Triggered Sense-Amplifier Flip-Flop-Based Driving Circuit For Glitch-Free Nand-Based Dcdl International Journal of Scientific Research, Vol.III, Issue. V, May 2014

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