Volume : IV, Issue : XI, November - 2015

VEDIC DIVIDER DESIGN AND SIMULATION USING REVERSIBLE LOGIC

Ms. Nikita N. Buradkar, Prof. Sanjay Tembhurne

Abstract :

 Everyday new technology is being developed which is fast, compact but more complex than its predecessors. The increase in frequency of clock to achieve greater speed of the system and increase in number of transistors which are embedded into a chip to achieve complexity of a conventional system results in increased power consumption. Almost all the gates used in the chip to perform logical operations in a conventional computer are irreversible. Reversible logic is gaining interest in the recent past due to less heat dissipating characteristics. It is proved that any Boolean function can be implemented using reversible gates. Every time a logical operation is performed some information about the input is erased or lost is dissipated as heat. Reversible logic circuits are increasingly used in power minimization. The hardware computation using regular that is irreversible gates results in power dissipation due to information loss. The methods of Vedic math has been the source of inspiration for many centuries in the field of computation. In the current binary world of high speed processing, it is necessary to have time and space efficient methods for performing arithmetic operations. Hence, in the proposed system we have designed reversible divider to reduce power dissipation while performing division.

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Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

Ms. Nikita N. Buradkar, Prof. Sanjay Tembhurne / VEDIC DIVIDER DESIGN AND SIMULATION USING REVERSIBLE LOGIC / International Journal of Scientific Research, Vol : 4, Issue : 11 November 2015

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