Volume : IV, Issue : I, January - 2015

VLSI Implementation of High performance 128–bit Binary adder

Angom Sachindro Singh, Dr. P. Sreevani

Abstract :

In this paper, a novel quantum-dot cellular automata(QCA) adder design is presented that decrease the number ofQCA cells compared to previously report designs. Theproposed one-bit QCA adder design is based on a newalgorithm that requires only three majority gates and twoinverters for the QCA addition.A novel 128-bit adder designed in QCA was implemented. It achieved speed performances higher than all the existing. QCA adders, with an area requirement comparable with the cheap RCA and CFA established. The novel adder operates in the RCA fashion, but it could propagate a carry signal through a number of cascaded MGs significantly lower than conventional RCA adders. In adding together, because of the adopted basic logic and layout strategy, the number of clock cycles required for completing the explanation was limited. As transistors reduce in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot find much smaller than their current size. The quantum-dot cellular automata approach represents one of the possible solutions in overcome this physical limit, even though the design of logic modules in QCA is not forever straightforward. Index Terms—Adders, nano-computing, QCA (quantum-dot cellular automata)

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Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

Angom Sachindro Singh,V.Sreevani VLSI Implementation of High performance 128-bit Binary adder International Journal of Scientific Research, Vol : 4, Issue : 1 January 2015

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