Volume : II, Issue : II, February - 2013

VLSI Motion Estimation Architecture for Full Search Block Matching Algorithm

Bhagavanreddy Thokala, K. Haripriya

Abstract :

This paper introduces a configurable motion estimation architecture for a wide range of fast block-matching algorithms (BMAs). Contemporary motion estimation architectures are either too rigid for multiple BMAs or the flexibility in them is implemented at the cost of reduced performance. The proposed architecture overcomes both of these limitations. The configurability of the proposed architecture is based on a new BMA framework that can be adjusted to support the desired set of BMAs. The chosen framework configuration is implemented by an intelligent control logic which is integrated to an efficient parallel memory system and distortion computation unit. The flexibility of the framework is demonstrated by mapping five different BMAs (BBGDS, DS, CDS, HEXBS, and TSS) to the architecture. The total execution time of the mapped BMAs is shown to be almost directly proportional to the number of tested checking points in the search area, so the architecture is very tolerant of different BMA-specific search strategies and search patterns. In addition, a run-time switching between supported BMAs can be done without performance compromises. With a 0.25-μm CMOS technology, the proposed architecture configured for FULLSEARCH, BBGDS, and TSS requires only 14.2 kgates and 2.5 KB of memory at 200 MHz operating frequency. A performance comparison to the reference programmable architecture sreveals that only the proposed implementation is able to process real-time (30 fps) fixed block-size motion estimation (1 reference frame) at full HDTV resolution (1920× 1080).

Keywords :

Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

Bhagavanreddy Thokala, K.Haripriya VLSI Motion Estimation Architecture for Full Search Block Matching Algorithm International Journal of Scientific Research, Vol.II, Issue.II February 2013

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