Comparison of Lower Power Vlsi Using Clocked Gate Style And Non–Clocked Style

R.GIRISRINIVAAS; G.LAKSHMI NARASIMHAN; M.GURU RAJKUMAR; P.DASS

Volume : V, Issue : II, February - 2015

Comparison of Lower Power Vlsi Using Clocked Gate Style And Non–Clocked Style

R. Girisrinivaas, G. Lakshmi Narasimhan, M. Guru Rajkumar, P. Dass

Abstract :

In present world VLSI technology energy consumption is an important factor to be considered among other factors like area occupation,performance and speed of the portable devices. The reduction in size and complexity of the portable devices have resulted in very large amount of power wastage in the devices .Due to this pneumonia low power VLSI designs have become very important part of portable devices. There is more strategy for designing the lower power VLSI. In this paper I have compared only 2 methods of designing the lower power VLSI using clocked logic style and non–clocked logic style. It minimizes the power wastage by controlling the clock whenever the clock is not used. Merge and Split concepts were applied in clocked gating style design to reduce power wastage. Experimental output show that these designs achieves low power wastage. In non–clocked logic style different method are compared by testing transistor level simulations for half adder circuit using Eldo simulator of Mentor graphics.