Design and Implementation of High–performance Logic Arithmetic Full Adder Circuit based on FinFET Technology – Shorted Gate Mode

Sarita Chauhan; Mamta kasotiya; Nishi chouhan; Sheetal Mundra; ShivangiAgarwal

Volume : VII, Issue : V, May - 2017

Design and Implementation of High–performance Logic Arithmetic Full Adder Circuit based on FinFET Technology – Shorted Gate Mode

Sarita Chauhan, Mamta Kasotiya, Nishi Chouhan, Sheetal Mundra, Shivangiagarwal

Abstract :

Fin–type ﬁeld–effect transistors (FinFETs) are promising substitutes for bulk CMOS at the Nano scale. FinFETs are double gate and multi–gate devices. Double–gate (DG) FinFETs has better Short Channels Effects (SCEs) performance compared to the conventional CMOS and stimulates technology scaling. The two gates of a FinFET can either be shorted for higher performance or independently controlled for lower leakage or reduced transistor count. In this paper, we are designing a Double–gate (DG) FinFETs and extracting their transfer characteristics by using Synopsys TANNER–EDA simulation tool. Full Adder is implemented in CMOS with technology and FinFET–shorted gate mode with technology along with its working waveform and performance analysis. TANNER–EDA simulations are carried out for the design and results are analyzed.