Design Of High–Speed, Low–Power Frequency Dividers For High Speed Frequency Synthesizer In 0.18Â�m Cmos Process

Aniruddha C. Kailuke; Pankaj Agrawal; R. V. Kshirsagar

Volume : VI, Issue : IV, April - 2016

Design Of High–Speed, Low–Power Frequency Dividers For High Speed Frequency Synthesizer In 0.18Â�m Cmos Process

Aniruddha C. Kailuke, Pankaj Agrawal, R. V. Kshirsagar

Abstract :

The CMOS technologies offer the high speed and low power dissipation which is required in multigigahertz communication systems such as optical data links and wireless products. This paper will cover design tradeoffs in frequency divider which are maximum operating frequency, power consumption and number of transistors needed. Analog approach is adopted in design of Frequency divider. The design of communication circuits, namely a 1/2 frequency divider is faicated using a 0.18μm CMOS process. The divider achieves a maximum speed of ~3GHz with a power dissipation of 1mW.