Volume : V, Issue : VI, June - 2015

IMPROVING THE RELIABILTIY OF a SOC BY TEST HOLE REDUCTION METHODOLOGIES

Soumya Hegde, Prof. K. N Rajarao

Abstract :

 Manufacturing defects can be minimized but cannot be avoided during manufacturing process. Commonly found manufacturing defects are open interconnect on the die due to dust particles; short–circuited source or drain on the transistor due to metal spike–through etc.Testability measures how easy it is to create a program to test a manufactured design’s quality. Two types of tests for silicon devices are functional test and structural test. Functional testing ensures that functionality device is proper. Structural test makes sure that all transistors are present, connected correctly, and are operating as expected. Design for Testability (DFT) on–die is necessary to meet the above mentioned features. The areas which cannot be tested by structural testing in a pre–silicon environment are called ‘Test holes’, which requires functional test cases to ensure the logic inside the test holes are defect free. Lesser the pre silicon test holeslower the testing cost of aSoC and easier the post silicon testing process. The structural testing, which avoids the tedious functional testing is given more importance in most. In this paper, different methodologies to reduce the test holes using structural design are attempted. This methods helps to improve the time to market by cutting down on functional validation on each of the die, to meet the desired DPM(defect per million).

Keywords :

Article: Download PDF   DOI : 10.36106/ijar  

Cite This Article:

Soumya Hegde, Prof. K.N RajaRao Improving the Reliabiltiy of a SOC by Test Hole Reduction Methodologies Indian Journal of Applied Research, Vol.5, Issue : 6 June 2015

Number of Downloads : 608

References :