LOW POWER AND LOW CMOS COMPLEXITY BASED COMPOSITE S–BOX FOR AES ENCRYPTION AND AES DECRYPTION

K. Sandyarani; Dr. P.Nirmal Kumar

Volume : V, Issue : X, October - 2015

LOW POWER AND LOW CMOS COMPLEXITY BASED COMPOSITE S–BOX FOR AES ENCRYPTION AND AES DECRYPTION

K. Sandyarani, Dr. P. Nirmal Kumar

Abstract :

The substitution–box(s–box) is a basic component of symmetric key algorithms which performs substitution. This paper presents low power architecture for composite field arithmetic based Sub Bytes transformation (S–Box) used in Advanced Encryption Standard (AES) encryption. AES is more secure than Data Encryption Standard (DES). It supports large key sizes such as 128, 192 and 256 key sizes. AES is faster in both hardware and software. The S–box and Inverse S–box utilizes a low power 2–input XOR gate with only six devices to achieve a compact module implemented in 250nm IBM CMOS technology. In the proposed method, composite S–box is designed using Tanner 14.1i design tool. In order to reduce the hardware complexity and power consumption of AES Encryption and Decryption, Tanner design tool is preferred by the current research work. This design indicates power dissipation only around 0.0923µW using a 0.8v supply voltage and it is suitable for applications such as RFID tags and smart cards which require low power consumption with small silicon die.