Volume : III, Issue : X, October - 2013

Performance Evaluation of 6T Sram Cell Structure and Peripheral Circuitry

Prachi Jain, Neetu Singh Chouhan

Abstract :

Memory is the most important building block in rapid development of digital designs as half of the silicon area is used to store data value and program instructions.. The power consumption and speed of SRAMs are important issue that has lead to multiple designs with the purpose of minimizing the power consumption. Bipolar SRAM is faster than that of CMOS SRAM because of small voltage swing on bit–lines also the VBE of bipolar transistor is 0.8 volts, so it requires less time to sense whatever data is stored in the memory. The major constraint of bipolar SRAM is larger power dissipation and complicated control signaling as there is small voltage variation. . CMOS SRAM is preferred over MOS type when large size memory is required, as in CMOS logic there is no static power dissipation. Power is dissipated only in case of change of state in CMOS SRAM. Major portion of memory chip is taken up by cell array, so if cell size can be reduced we can have smaller area. This paper focuses on the read and writes operation of 6t SRAM cell and peripheral circuitry such as row address decoder, column multiplexer, sense amplifier which are main building blocks of SRAM cell. The peripheral circuitry has a tremendous impact on the robustness, performance, and power consumption of the memory unit so careful analysis of the options and consideration of periphery design is appropriate.

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Article: Download PDF   DOI : 10.36106/ijar  

Cite This Article:

Prachi Jain, Neetu Singh Chouhan / Performance Evaluation of 6T Sram Cell Structure and Peripheral Circuitry / Indian Journal of Applied Research, Vol.3, Issue.10 October 2013

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